This disclosure relates to debugging peripheral circuits, such as processors, on an integrated circuit chip. The disclosure is particularly relevant to debugging peripheral circuits which form part of a System-on-Chip (SoC).
In the past, an embedded system which had multiple core devices (processors, memories etc.) would have been incorporated onto a Printed Circuit Board (PCB) and connected on the PCB via buses. Traffic in the embedded system was conveyed over these buses. This arrangement was convenient for debugging the core devices, because debugging tools such as oscilloscopes and logic analyzers could be attached to the PCB's buses allowing direct access to the core devices.
Market demand for smaller products coupled with advances in semiconductor technology has led to the development of System-on-Chip (SoC) devices. In a SoC, the multiple core devices of an embedded system are integrated onto a single chip. In a SoC, the traffic in the embedded system is conveyed over internal buses, thus connection of debugging tools directly to the system bus is no longer possible. The resulting reduced access coupled with an increasing quantity of data being transported around the chip (due to developments of SoC technology leading to integration of multiple processing cores and higher internal clocking frequencies), has reduced the ability of external debugging tools to find and solve bugs within the system in the timescales demanded by the industry.
Thus, the development of SoC devices required associated development in debugging technology, which led to the integration of some debug functionality onto the SoC. It is now customary for each core device to have an associated debug unit. Typically, the debug unit can manipulate the operation of the core device (e.g. start/stop the core device), and also collect trace data from that core device. The collected debug information is then funneled off chip via a debug port to external debugging tools. Whilst these developments have improved debugging of SoC devices, that debugging is generally limited to independent monitoring and assessment of the individual cores. This is typically because different manufacturers supply the core devices which a SoC manufacturer then embeds onto the SoC. Each manufacturer supplies its core device with an associated debug unit, which is configured to communicate with external debugging tools to debug that core device. For a multiple core SoC, the total cost in terms of silicon area for provision of debug units and debug ports for each core device is undesirably high. Additionally, even with such a debug architecture in place, complete system-level debug is still not achievable.
Thus, there is a need for an improved debug architecture for debugging SoC devices.